The present invention relates to integrated circuit devices, and more particularly to integrated circuit memory devices and methods of operating integrated circuit memory devices.
Integrated circuit memory devices are widely used in consumer and commercial applications. One widely used integrated circuit memory device is, for example, synchronous Dynamic Random Access Memory devices (synchronous DRAM devices). Synchronous DRAMs may be used for the main memory of a computer system, and also may be used in graphics applications.
In a conventional DRAM device, a precharge command PRE turns off an active word line and restores a default voltage level on bit lines of the DRAM device. Before a word line is turned off, memory cells connected to that word line should have a valid voltage level. Valid voltage levels for interfaces of DRAM circuits are described, for example, in Intel Corporation""s PC SDRAM Specification, Revision 1.7, November, 1999, hereinafter referred to as the PC-100 Specification.
To help ensure that memory cells connected to the word line have a valid voltage level, conventional DRAM devices are typically subject to timing constraints known as write back timing and write recovery. Write back timing constraints describe timing requirements after a word line activation. The write back timing requirements are generally analog and may be determined based on factors such as the physical characteristics of a memory cell, and sizing of a sense amplifier. Write recovery timing constraints describe timing requirements after a write command is sent to memory cells that are coupled to an already active word line. Write recovery timing requirements typically consist of a digital and an analog component. The digital component is based on write latency and burst length values. This delay can be expressed in terms of clock cycles and is therefore a function of the clock frequency. The analog component is based on physical delays resulting from input data latching to memory cells. The dominant portion of this analog write delay is typically the time that is needed to change the charge being stored inside the memory cells from the old to the new voltage level. This charging or discharging operation is similar to the charging or discharging of a capacitor through a resistor device. Therefore, this delay is independent of the clock frequency the DRAM device is operated at and hereby represents a delay that has a fixed value in real time (i.e., analog portion). Thus, conventional DRAM devices must comply with strict timing constraints when issuing a precharge command PRE. Unfortunately, those timing constraints can limit the usage of the command bus, for reasons some of which will be described below.
Referring now to FIG. 1A, external commands and addresses are input into the global DRAM control 101, which generates one of a precharge command and a precharge-all command along with appropriate bank addresses that are sent to a plurality of memory banks. Here, two memory banks, Bank A and B, are shown for purposes of simplicity, however, any number of memory banks could theoretically be employed in the same manner.
In conventional DRAM devices operating according to the PC-100 Specification, execution of either the precharge command or the precharge-all command is fixed with respect to a bank activation command ACT and a write command WRT, as will now be described below in conjunction with FIG. 1B. FIG. 1B shows a timing diagram of a precharge command PRE in a conventional DRAM device having a single bank configuration. In this example, it is presumed that a burst length BL is equal to four clock cycles, meaning that four data bits per data I/O are transferred from or to the DRAM device with each read or write command, respectively. As shown in FIG. 1B, a bank activation command ACT, which is also known as row address strobe (RAS) signal, is spaced apart from a precharge command PRE tRAS which here is by five clock cycles, the minimum write back timing requirement under the PC-100 Specification. Similarly, a write command WRT, which is also known as the column address strobe (CAS) signal with the write mode being activated, is also spaced apart from the precharge command PRE by five clock cycles, the minimum write recovery timing requirement under the PC-100 Specification. Thus, due to the timing requirements of the PC-100 Specification, a relatively large number of clock cycles can pass after the write command WRT or the bank activation command ACT before the precharge command is executed. Unfortunately, this fixed execution of the precharge command can limit the usage of a command bus since the command bus is shared between more than one bank.
Because the timing requirements can force fixed execution of the precharge command, conflicts on the command bus can result that may undesirably degrade system performance. As shown in FIG. 2, a potential conflict on the command bus of a conventional DRAM device can result. This example again assumes that a burst length BL is equal to 4. In this example, a memory controller that controls the DRAM device attempts to perform an external precharge command PRE on Bank A after a write command WRT has been executed. Due to this write recovery restriction of the PC-100 specification, a precharge command PRE is scheduled at a minimum of at least five clock cycles after the write command VVRT. Since a conflict might occur on the command bus, the write recovery restriction can preemptively restrict future usage of the command bus if the write command WRT at Bank B occurs simultaneously with the precharge command PRE at Bank A.
Fixed execution of the precharge-all command PRE-ALL with respect to the bank activation command ACT can also limit usage of banks that have been activated at an earlier time. As shown in FIG. 3, a precharge-all command PRE-ALL is executed to deactivate different word lines in banks that are currently open. However, under the PC-100 Specification, the timing requirements of a write back timing parameter tRAS, require that the precharge-all command PRE-ALL be issued after at least five clock cycles have passed since the last bank activation command ACT. Thus, when bank activation commands ACT are issued in close proximity to different banks, for example Bank A and Bank B, this write back timing requirement can limit the usage of banks that have been activated earlier since clock cycles can be lost so that the precharge-all command PRE-ALL is executed simultaneously on all banks. In conventional DRAM circuits, the precharge-all command PRE-ALL can also undesirably cause a high peak power consumption since active word lines are shut off at the same time and bit line precharging circuits are turned on at the same time.
Furthermore, as shown in FIG. 4, conventional DRAM devices operating according to the PC-100 Specification allow for only one possible timing pattern that fulfills all timing requirements for minimum row cycle time (or random access time) tRC. Accordingly, it may be desirable to provide improved integrated circuit devices that are more flexible in execution of precharge and/or precharge-all commands.
An aspect of the present invention can provide integrated circuit memory devices that include a memory array including at least one memory bank, and a pair of input/output lines coupled to the memory array, wherein each of the memory banks includes a local precharge control unit that can enhance system performance. The local precharge control unit can generate a precharge request that is then used in execution of a local precharge command to a specific memory bank.
According to another aspect of the invention, each of the local precharge control units may comprise, for example, means for generating a precharge request. The precharge request can then be used to execute a local precharge bank command without timing restrictions with respect to one of the external precharge command and the external precharge-all request, respectively. The means for generating generates a precharge request based on one of an external precharge command and an external precharge-all command.
According to another aspect of the invention, each of the local precharge control units may also comprise means for posting that is responsive to an indication that at least one specified timing requirement has been satisfied for at least that memory bank. The means for posting xe2x80x9cpostsxe2x80x9d or delays execution of the precharge request, such that issuance of the local precharge bank command is delayed until the indication that at least one specified timing requirement has been satisfied for at least that memory bank is provided to the means for posting.
According to another aspect of the invention, the means for posting can also include means, responsive to the precharge request and to the indication that at least one specified timing requirement has been satisfied for at least that memory bank, for executing a local precharge bank command at any time without timing restrictions with respect to the precharge request when the means for executing receives the indication that specified timing requirements are satisfied for at least that memory bank.
The local precharge control unit can allow the local precharge bank request to be generated immediately after one of an external precharge command and an external precharge-all command is generated. As such, the local precharge bank request may be generated without timing restrictions with respect to other external commands. As such, the local precharge bank request can be generated at any time after a write command without a write back timing limitation and/or write recovery timing limitation with respect to one of the external precharge command and the external precharge-all command.
The local precharge control unit can also allow timing of one of the external precharge command and the external precharge-all command with respect to one of an external write command and an external bank activation command to not be subject to one of a write recovery timing limitation and a write back timing limitation, respectively. As such, spacing between one of the precharge command and the precharge-all command and a write command can be adjustable to provide variable spacing between the one of the precharge command and the precharge-all command and the write command. Moreover, spacing between one of the precharge command and the precharge-all command and a bank activation command can also be adjustable to provide variable spacing between a bank activation command and one of the precharge command and the precharge-all command. By contrast, spacing of the local precharge bank command may be fixed with respect to the bank activation command.
In comparison to conventional DRAM integrated circuit devices, aspects of the embodiments described-above can provide improved system performance. By removing timing restrictions that are normally present during execution of one of the external precharge command and the external precharge-all command, more flexible utilization of the command bus can be provided. Moreover, data bus utilization can also improved since more opportunities to issue read or write commands for the data bus are generated. Finally, the number of power consumption peaks can also be reduced. These improvements with respect to command bus and data bus utilization can lead to overall improvements in system performance.
An aspect of the present invention may also include methods of operating an integrated circuit memory device in which local precharge bank commands are generated in the memory device. In particular, a precharge request can be generated that is used to execute a local precharge bank command. The precharge request can be posted responsive to one of an external precharge command and an external precharge all command. Posting may comprise holding the precharge request until the indication is provided that the at least one specified timing requirement has been satisfied for at least that memory bank indicating that specified timing requirements are fulfilled. Alternatively, posting may comprise sampling and storing the precharge request, and holding execution of the stored precharge request until the holding means receives the indication. In either case, execution of the local precharge bank command can be delayed until the indication is provided that the at least one specified timing requirement has been satisfied, for at least that memory bank. The local precharge bank command can then be executed responsive to the precharge request and to the indication that the at least one specified timing requirement has been satisfied for at least that memory bank.